Nanosheet metal-oxide semiconductor field effect transistor with asymmetric threshold voltage

ABSTRACT

A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.

BACKGROUND

The present invention generally relates to the field of complementarymetal-oxide semiconductor field effect transistor (MOSFET) devices, andmore particularly to nanosheet MOSFETs having an asymmetric thresholdvoltage.

In contemporary semiconductor device fabrication processes a largenumber of semiconductor devices, such as field effect transistors(FETs), are fabricated on a single wafer. Non-planar devicearchitectures, including nanosheet FETs, provide increased devicedensity and increased performance over planar devices. In nanosheetFETs, in contrast to conventional FETs, the gate stack wraps around thefull perimeter of each nanosheet, enabling fuller depletion in thechannel region, and reducing short-channel effects. The wrap-around gatestructures used in nanosheet devices can also enable greater managementof leakage current in the active regions, even as drive currentincreases. However, the lateral asymmetric channel (LAC) doping profileused in planar FETs to improve electrical characteristics can bedifficult to achieve in stacked nanosheet FETs.

SUMMARY

According to an embodiment of the present disclosure, a method offorming a semiconductor structure includes forming a nanosheet stack ona substrate, the nanosheet stack including an alternating sequence ofsacrificial nanosheets and channel nanosheets, the sacrificialnanosheets including second nanosheets located between first nanosheetsand third nanosheets, the first nanosheets and the third nanosheetshaving a first germanium concentration that is lower than a secondgermanium concentration of the second nanosheets, and selectivelyetching the sacrificial nanosheets, wherein the lower first germaniumconcentration causes the first nanosheets and the third nanosheets to beetched slower than the second nanosheets creating an indentation regionon opposing sides of the nanosheet stack, the indentation region havinga narrowing shape towards remaining second nanosheets of the sacrificialnanosheets.

According to another embodiment of the present disclosure, a method offorming a semiconductor structure includes forming an inner spacerbetween channel nanosheets on a semiconductor substrate, a first portionof the inner spacer is located on a first side of the semiconductorstructure and a second portion of the inner spacer is located on asecond side of the semiconductor structure opposing the first side, thefirst portion of the inner spacer on the first side including aprotruding region extending outwards from a middle top surface of thefirst portion of the inner spacer, and forming a metal gate stack indirect contact with the inner spacer, the first portion of the innerspacer including the protruding region pinching off the metal gate stackfor increasing a threshold voltage on the first side, the protrudingregion providing a T-shaped inner spacer with a space between theprotruding region and the channel nanosheets being less than twice athickness of an inner nitride layer in the metal gate stack.

According to another embodiment of the present disclosure, a method offorming a semiconductor structure includes forming a plurality ofchannel nanosheets above an isolation region on a semiconductorsubstrate, forming an inner spacer between each of the plurality ofchannel nanosheets, a first portion of the inner spacer is located on afirst side of the semiconductor structure, and a second portion of theinner spacer is located on a second side of the semiconductor structureopposing the first side, the first portion of the inner spacer on thefirst side including a protruding region extending outwards from amiddle top surface of the first portion of the inner spacer, and forminga metal gate stack separated from a source region located on the firstside and along sidewalls of the plurality of channel nanosheets by thefirst portion of the inner spacer, the metal gate stack being separatedfrom a drain region located on the second side and along opposingsidewalls of the plurality of channel nanosheets by the second portionof the inner spacer, the protruding region of the first portion of theinner spacer pinching off the metal gate stack for increasing athreshold voltage on the first side, the protruding region providing aT-shaped inner spacer with a space between the protruding region and thechannel nanosheets being less than twice a thickness of an inner nitridelayer in the metal gate stack.

According to yet another embodiment of the present disclosure, a methodof forming a semiconductor structure includes forming a nanosheet stackabove a substrate, the nanosheet stack including a channel nanosheetdisposed between a stack of sacrificial nanosheets, the stack ofsacrificial nanosheets including first sacrificial nanosheets disposedon opposite sides and in direct contact with the channel nanosheet,second sacrificial nanosheets in direct contact with a side of the firstsacrificial nanosheets opposing a side of the second sacrificialnanosheets in contact with the channel nanosheets and third sacrificialnanosheets above and in direct contact with the second sacrificialnanosheets, wherein the first sacrificial nanosheets and the thirdsacrificial nanosheets have a first germanium concentration that islower than a second germanium concentration of the second sacrificialnanosheets, selectively etching the stack of sacrificial nanosheets toform an indentation region, forming a first inner spacer partiallyfilling the indentation region, the first inner spacer being located onopposite sides of the second sacrificial nanosheets and between thefirst and third sacrificial nanosheets, selectively removing portions ofthe first and third sacrificial nanosheets, selectively removing thefirst inner spacer from a first side of the nanosheet stack, the firstinner spacer remaining on a second side of the nanosheet stack opposingthe first side, and depositing a second inner spacer on the first sideof the nanosheet stack, wherein outer portions of the second innerspacer is aligned with the channel nanosheet.

The method further includes conducting a replacement metal gate processon the semiconductor structure and removing the first inner spacer fromthe second side of the nanosheet stack before completing the replacementmetal gate process.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor structure depictinga nanosheet stack formed over a semiconductor substrate, according to anembodiment of the present disclosure;

FIG. 2 is a cross-sectional view of the semiconductor structure afterrecessing sacrificial nanosheets, according to an embodiment of thepresent disclosure;

FIG. 3 is a cross-sectional view of the semiconductor structure afterforming a first inner spacer, according to an embodiment of the presentdisclosure;

FIG. 4 is a cross-sectional view of the semiconductor structure afterremoving residual portions of the sacrificial nanosheets, according toan embodiment of the present disclosure;

FIG. 5 is a cross-sectional view of the semiconductor structure afterforming a protective organic planarization layer and removing portionsof the first inner spacer, according to an embodiment of the presentdisclosure;

FIG. 6 is a cross-sectional view of the semiconductor structure afterremoving the protective organic planarization layer and forming a secondinner spacer, according to an embodiment of the present disclosure;

FIG. 7 is a cross-sectional view of the semiconductor structure afterforming a source region and drain region, according to an embodiment ofthe present disclosure;

FIG. 8 is a cross-sectional view of the semiconductor structure afterremoving a dummy gate and the sacrificial nanosheets, according to anembodiment of the present disclosure;

FIG. 9 is a cross-sectional view of the semiconductor structure afterremoving remaining portions of the first inner spacer, according to anembodiment of the present disclosure; and

FIGS. 10A-10B depict cross-sectional views of the semiconductorstructure after depositing a gate stack and a metal fill, according toan embodiment of the present disclosure.

The drawings are not necessarily to scale. The drawings are merelyschematic representations, not intended to portray specific parametersof the invention. The drawings are intended to depict only typicalembodiments of the invention. In the drawings, like numbering representslike elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosedherein; however, it can be understood that the disclosed embodiments aremerely illustrative of the claimed structures and methods that may beembodied in various forms. This invention may, however, be embodied inmany different forms and should not be construed as limited to theexemplary embodiments set forth herein. In the description, details ofwell-known features and techniques may be omitted to avoid unnecessarilyobscuring the presented embodiments.

For purposes of the description hereinafter, terms such as “upper”,“lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing figures. Terms such as “above”,“overlying”, “atop”, “on top”, “positioned on” or “positioned atop” meanthat a first element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure may be present between the first element andthe second element. The term “direct contact” means that a firstelement, such as a first structure, and a second element, such as asecond structure, are connected without any intermediary conducting,insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

It is understood that although the disclosed embodiments include adetailed description of an exemplary nanosheet FET architecture havingsilicon and silicon germanium nanosheets, implementation of theteachings recited herein are not limited to the particular FETarchitecture described herein. Rather, embodiments of the presentinvention are capable of being implemented in conjunction with any othertype of FET device now known or later developed.

As integrated circuit fabrication continues to strive to produce smallerand denser integrated circuits, a viable alternative for 5 nm nodetechnology and beyond includes nanosheet FETs. As previously described,the gate stack in nanosheet FETs wraps around the full perimeter of eachnanosheet, enabling fuller depletion in the channel region, and reducingshort-channel effects, among other benefits. This allows an increaseddevice density and an increased performance over planar devices.

Nanosheet FETs often include thin alternating layers (nanosheets) ofdifferent semiconductor materials arranged in a stack. Typically,nanosheets are patterned into nanosheet fins. Once the nanosheet finsare patterned, a gate stack is formed over a channel region of thenanosheet fins, and source/drain regions are formed adjacent to the gatestack. In some devices, once the gate stack or the source/drain regionshave been formed, an etching process is performed to selectively removenanosheet layers of one of the dissimilar materials from the fins. Theetching process results in the undercutting and suspension of the layersof the nanosheet fin to form nanosheets or nanowires that can be used toform gate-all-around devices.

In traditional MOSFETs manufacturing, a lateral asymmetric channel (LAC)doping profile approach is implemented to improve device's electricalcharacteristics. For LAC MOSFETs, the doping concentration at the sourceside of the channel region is higher than that of the drain side. Thus,the non-uniform channel doping causes the channel potential transitionat the source side of the channel region being much steeper than that ofthe drain side while the device is operating. Such a steep potentialdistribution near the source side of the channel region enhances thelateral channel electric field, and thus increases carrier mobility.However, implementing a non-uniform channel doping profile instate-of-the-art short channel devices (e.g., nanosheets) can be verychallenging due to the reduced device area. Thus, there is a need foralternative designs and techniques for introducing a halo region in aportion of the channel in a self-aligned manner in stacked nanosheetFETs.

Therefore, embodiments of the present disclosure provide a stackednanosheet complementary metal oxide semiconductor (CMOS) structure inwhich an asymmetric threshold voltage distribution across the channelregion is achieved by pinching off a work function metal near the sourceside of the channel region. The resulting asymmetric work function metaldistribution improves device performance by increasing threshold voltageon the source side of the channel region without requiring metal gatepatterning. One way to pinch-off the work function metal to achieve theasymmetric threshold voltage distribution across the channel includesforming asymmetric inner spacers. Embodiments by which the asymmetricinner spacers can be formed to achieve a stacked nanosheet structurewith asymmetric threshold voltage distribution are described in detailedbelow by referring to the accompanying drawings in FIGS. 1-10B.

Referring now to FIG. 1 , a cross-sectional view of a semiconductorstructure 100 including a nanosheet stack 108 is shown, according to anembodiment of the present disclosure. The nanosheet stack 108 is formedfrom an alternating sequence of silicon germanium (SiGe) sacrificialnanosheets 110, 112, 114 (hereinafter “sacrificial nanosheets”) andsilicon (Si) channel nanosheets 120 (hereinafter channel nanosheets”).The nanosheet stack 108 is formed on an oxide isolation layer 106, whichis formed on a semiconductor substrate 102 (e.g., silicon). For ease ofillustration, without intent of limitation, a sequence of fifteenalternating sacrificial nanosheets 110, 112, 114 and channel nanosheets120 is shown in FIG. 1 . However, any number of sacrificial nanosheets110, 112, 114 and channel nanosheets 120 can be formed in thesemiconductor structure 100 to satisfy design requirements.

In one or more embodiments, the alternating sequence of sacrificialnanosheets 110, 112, 114 and channel nanosheets 120 are formed byepitaxially growing one layer and then the next until the desired numberand desired thicknesses of the nanosheets are achieved. Epitaxialmaterials can be grown from gaseous or liquid precursors. Epitaxialmaterials can be grown using vapor-phase epitaxy (VPE), molecular-beamepitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process.Epitaxial silicon, silicon germanium, and/or carbon doped silicon (Si:C)silicon can be doped during deposition (in-situ doped) by addingdopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants(e.g., boron or gallium), depending on the type of transistor.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases are controlled and the systemparameters are set so that the depositing atoms arrive at the depositionsurface of the semiconductor substrate with sufficient energy to moveabout on the surface such that the depositing atoms orient themselves tothe crystal arrangement of the atoms of the deposition surface.Therefore, an epitaxially grown semiconductor material has substantiallythe same crystalline characteristics as the deposition surface on whichthe epitaxially grown material is formed. For example, an epitaxiallygrown semiconductor material deposited on a {100} orientated crystallinesurface will take on a {100} orientation. In some embodiments, epitaxialgrowth and/or deposition processes are selective to forming onsemiconductor surfaces, and generally do not deposit material on exposedsurfaces, such as silicon dioxide or silicon nitride surfaces.

In some embodiments, the gas source for the deposition of epitaxialsemiconductor material include a silicon containing gas source, agermanium containing gas source, or a combination thereof. For example,an epitaxial silicon layer can be deposited from a silicon gas sourcethat is selected from the group consisting of silane, disilane,trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane,dichlorosilane, trichlorosilane, methylsilane, dimethylsilane,ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane andcombinations thereof. An epitaxial germanium layer can be deposited froma germanium gas source that is selected from the group consisting ofgermane, digermane, halogermane, dichlorogermane, trichlorogermane,tetrachlorogermane and combinations thereof. While an epitaxial silicongermanium alloy layer can be formed utilizing a combination of such gassources. Carrier gases like hydrogen, nitrogen, helium, and argon can beused.

According to an embodiment, (first or bottom) sacrificial nanosheets 110and (third or top) sacrificial nanosheets 114 include silicon germanium(SiGe) with a first germanium (Ge) concentration of approximately 25%Ge, while (second or middle) sacrificial nanosheets 112 located betweenthe sacrificial nanosheets 110 and the sacrificial nanosheets 114 areformed with a second germanium concentration of approximately 35% Ge.The different Ge concentrations allows to have different etch ratesbetween sacrificial nanosheets 110, 114 and sacrificial nanosheets 112,as will be described in detail below.

According to an embodiment, known processing techniques have beenapplied to the alternating sequence of sacrificial nanosheets 110, 112,114 and channel nanosheets 120 forming the nanosheet stack 108. Forexample, the known processing techniques can include the formation offin hard masks (not shown) over the nanosheet stack 108. The fin hardmasks can be formed by first depositing the hard mask material (forexample silicon nitride) onto the nanosheet stack 108 using, forexample, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) orany suitable technique for dielectric deposition. The deposited hardmask material is then patterned into a plurality of individual fin hardmasks. The patterning of the hard masks is commensurate with a desiredfootprint and location of the channel nanosheets 120, which will be usedto form the channel regions of the semiconductor device. According to anexemplary embodiment, reactive ion etching (RIE) is used to etch throughthe alternating sequence of sacrificial nanosheets 110, 112, 114 andchannel nanosheets 120 to form the nanosheet stack 108 as illustrated inFIG. 1 .

With continued reference to FIG. 1 , a dummy gate 130 and a hard mask(HM) 140 are formed over and around the nanosheet stack 108.Specifically, as known by those skilled in the art, the dummy gate 130is formed over a top and sidewalls (not shown) of the nanosheet stack108. In one or more embodiments, the dummy gate 130 is formed fromamorphous silicon (a-Si), and the hard mask 140 is formed from siliconnitride (SiN), silicon oxide, an oxide/nitride stack, or similarmaterials and configurations. The hard mask 140 is typically formed overthe dummy gate 130 to act as an etch stop.

As depicted in the figure, offset spacers 150 have been formed alongsidewalls of the dummy gate 130 and hard mask 140. Offset spacers 150can be formed using a spacer pull down formation process. Offset spacers150 can also be formed using a sidewall image transfer (SIT) spacerformation process, which includes spacer material deposition followed bydirectional RIE of the deposited spacer material. The width dimensionsof the offset spacers 150 are chosen such that the offset spacers 150and the hard mask 140 define an initial width (w).

As known by those skilled in the art, the offset spacers 150 are used asa mask, to recess portions of the sacrificial nanosheets 110, 112, 114and the channel nanosheets 120 that are not under the offset spacers 150and dummy gate 130, as illustrated in the figure. For example, a RIEprocess can be used to recess the portions of the sacrificial nanosheets110, 112, 114 and the channel nanosheets 120 that are not under theoffset spacers 150 and dummy gate 130. Although not depicted, typicallythe sacrificial nanosheets 110, 112, 114 and the channel nanosheets 120are recessed into the oxide isolation layer 106 forming a trench (notshown). Because the fin etch is being performed before the dummy gatereplacement steps (described in detail below), the semiconductor devicefabrication processes described herein can be referred to as a fin firstprocess.

Referring now to FIG. 2 , a cross-sectional view of the semiconductorstructure 100 after recessing sacrificial nanosheets 110, 112, 114 isshown, according to an embodiment of the present disclosure. In thisembodiment, an isotropic etch process such as, for example, a hydrogenchloride (HCL) gas isotropic etch can be performed on the semiconductorstructure 100 to recess sacrificial nanosheets 110, 112, 114.Preferably, the selected isotropic etch process is capable of etchingsilicon germanium without attacking silicon.

As mentioned above, the germanium concentration in the sacrificialnanosheets 110, 114 is less than the germanium concentration in thesacrificial nanosheets 112. Thus, during the etching process thesacrificial nanosheets 112 formed with higher germanium concentrationare etched faster than the sacrificial nanosheets 110, 114 formed withlower germanium concentration. This causes a deeper recess orindentation region 202 into the sacrificial nanosheets 112, as depictedin the figure. Stated differently, because of the lower germaniumconcentration of the sacrificial nanosheets 110, 114, these layers areetched slower than the sacrificial nanosheets 112 creating theindentation region 202. It should be noted that regions 204 containingremaining portions of silicon germanium from the sacrificial nanosheets110, 114 can still be present in the semiconductor structure 100 afterthe etching process. The etch rate difference between the sacrificialnanosheets 110, 114 and the sacrificial nanosheets 112 naturally causesthe indentation region 202 to have a narrowing shape towards thesacrificial nanosheets 112, as illustrated in the figure.

Referring now to FIG. 3 , a cross-sectional view of the semiconductorstructure 100 after forming a first inner spacer 320 is shown, accordingto an embodiment of the present disclosure. In this embodiment, thefirst inner spacer 320 can be formed, for example, by conformaldeposition of an inner spacer material that pinches off the indentationregion 202 (FIG. 2 ). The inner spacer material forming the first innerspacer 320 includes, for example, silicon dioxide (SiO₂).

An isotropic etching, such as wet etching, is then performed to recessthe first inner spacer 320, as depicted in the figure. Recessing of thefirst inner spacer 320 exposes remaining portions of the sacrificialnanosheets 110, 114 (e.g., regions 204 in FIG. 2 ) located below theoffset spacers 150 and on the channel nanosheets 120. It should be notedthat excessive inner spacer material from other regions of thesemiconductor structure 100 can be removed during the isotropic etchingprocess.

Referring now to FIG. 4 , a cross-sectional view of the semiconductorstructure 100 is shown after removing residual portions of thesacrificial nanosheets 110, 114 below the offset spacers 150 and on thechannel nanosheets 120 exposed after recessing the first inner spacer320, according to an embodiment of the present disclosure.

As depicted in the figure, exposed remaining portions of the sacrificialnanosheets 110, 114 located below the offset spacers 150 and on thechannel nanosheets 120 are selectively removed from the semiconductorstructure 100 (i.e., from exposed areas of regions 204 in FIG. 2 ) toprevent SiGe release damage to subsequently formed source/drain epiregions. In an exemplary embodiment, an isotropic etch process such as,for example, a hydrogen chloride (HCL) gas isotropic etch can beconducted to remove exposed residual portions of the sacrificialnanosheets 110, 114 below the offset spacers 150 and on the channelnanosheets 120. Portions of the sacrificial nanosheets 110, 114 mayremain in contact with the dummy gate 130, inner regions of the channelnanosheets 120 and oxide isolation layer 106, as depicted in the figure.

Referring now to FIG. 5 , a cross-sectional view of the semiconductorstructure 100 is shown after forming a protective organic planarizationlayer (OPL) 520 and removing portions of the first inner spacer 320 froma first side of the semiconductor structure 100 opposing the protectiveOPL 520, according to an embodiment of the present disclosure.

The protective OPL 520 is formed by depositing an organic planarizingmaterial that is capable of effectively preventing damage of underlyinglayers during subsequent etching processes. According to an embodiment,protective OPL 520 protects a second side of the semiconductor structure100 opposing the first side during an etching process used to remove thefirst inner spacer 320 from the first side of the semiconductorstructure 100, as depicted in the figure. As will be explained below, asource drain region is formed on the first side of the semiconductorstructure 100, while a drain region is formed on the opposing secondside of the semiconductor structure 100.

The protective OPL 520 can include, but is not necessarily limited to,an organic polymer including C, H, and N. According to an embodiment,the OPL material can be free of silicon (Si). According to anotherembodiment, the OPL material can be free of Si and fluorine (F). Asdefined herein, a material is free of an atomic element when the levelof the atomic element in the material is at or below a trace leveldetectable with analytic methods available in the art. Non-limitingexamples of the OPL material forming the protective OPL 520 can includeJSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similarcommercially available materials. The protective OPL 520 may bedeposited by, for example, spin coating followed by a planarizationprocess, such as chemical mechanical polishing (CMP).

After forming the protective OPL 520, portions of the first inner spacer320 are selectively removed using, for example, a wet etching process,such as diluted HF. Removing portions of the first inner spacer 320 fromthe first side of the semiconductor structure 100 creates first recesses510. After removing the portions of the first inner spacer 320 from thefirst side of the semiconductor structure 100, the protective OPL 520 isremoved, as depicted in FIG. 6 .

Referring now to FIG. 6 , a cross-sectional view of the semiconductorstructure 100 after removing the protective OPL 520 and forming a secondinner spacer 640 is shown, according to an embodiment of the presentdisclosure. In an embodiment, the protective OPL 520 can be removedusing, for example, an OPL RIE including a trace point detection.

Similar to the first inner spacer 320, the second inner spacer 640 canbe formed by conformal deposition of an inner spacer material. Accordingto an embodiment, the inner spacer material forming the second innerspacer 640 includes, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN,SiOCN, SiOxNy, and combinations thereof. Etching processes includingRIE, wet etch, or isotropic vapor phased dry etch can be conducted toremove excess inner spacer material from the semiconductor structure100.

It should be noted that the second inner spacer 640 constitutes the maininner spacer for the semiconductor structure 100. In one or moreembodiments, the spacer material forming the first inner spacer 320 isselected based on providing etch selectivity to the spacer materialforming the second inner spacer 640. As depicted in the figure, thesecond inner spacer 640 on the first side of the semiconductor structure100 substantially fills the first recesses 510 (FIG. 5 ) whichcorresponds to the indention region 202 shown in FIG. 2 .

As shown in the figure, second inner spacer 640 includes a protrudingregion 612 extending outwards from a middle top surface of the innerspacer 640 towards the remaining sacrificial nanosheets 112. Theprotruding region 612 provides a T-shaped inner spacer formed in a waysuch that a space between the protruding region 612 and the channelnanosheets 120 is less than twice a thickness of a subsequently formednitride layer (e.g., inner nitride layer 1010 shown in FIG. 10A). Theresulting asymmetric shape of the second inner spacer 640 can pinch offthe subsequently formed nitride layer on the first or source side of thesemiconductor structure 100, as will be described in detail below.

In an exemplary embodiment, a thickness of the second inner spacer 640can vary between approximately 5 nm to approximately 10 nm, and rangesthere between, although a thickness less than 5 nm and greater than 10nm may be acceptable. A thickness of the protruding region 612 of thesecond inner spacer 640 can vary between approximately 2 nm toapproximately 5 nm, although a thickness less than 2 nm and greater than5 nm may be acceptable.

Referring now to FIG. 7 , a cross-sectional view of the semiconductorstructure 100 after forming source region 720 and drain region 722 isshown, according to an embodiment of the present disclosure.

At this step of the manufacturing process, source region 720 and drainregion 722 are formed using an epitaxial layer growth process on theexposed ends of the channel nanosheets 120. In-situ doping (ISD) orex-situ doping can be applied to dope the source region 720 and drainregion 722, thereby creating the necessary junctions of thesemiconductor device. Virtually all semiconductor transistors are basedon the formation of junctions. Junctions are capable of both blockingcurrent and allowing it to flow, depending on an applied bias. Junctionsare typically formed by placing two semiconductor regions with oppositepolarities into contact with one another. The most common junction isthe p-n junction, which consists of a contact between a p-type piece ofsilicon, rich in holes, and an n-type piece of silicon, rich inelectrons. N-type and p-type FETs are formed by implanting differenttypes of dopants to selected regions of the device to form the necessaryjunction(s). N-type devices can be formed by implanting arsenic (As) orphosphorous (P), and p-type devices can be formed by implanting boron(B).

It may be understood that the first side of the semiconductor structure100 corresponds to the side in which the source region 720 is located(i.e., source side). Similarly, the second side of the semiconductorstructure 100 (opposing the first side) corresponds to the side in whichthe drain region 722 is located (i.e., drain side).

After forming the source region 720 and the drain region 722, aninterlevel dielectric (ILD) layer 730 is formed to fill voids betweengate structures and other existing devices within the semiconductorstructure 100. The ILD layer 730 can be formed by, for example, CVD of adielectric material. Non-limiting examples of dielectric materials toform the ILD layer 730 may include silicon oxide, silicon nitride,hydrogenated silicon carbon oxide, silicon based low-k dielectrics,flowable oxides, porous dielectrics, or organic dielectrics includingporous organic dielectrics. After deposition of the ILD layer 730, a CMPprocess is conducted on the semiconductor structure 100 to expose a topsurface of the dummy gate 130, as depicted in the figure.

Referring now to FIG. 8 , a cross-sectional view of the semiconductorstructure 100 is shown after removing the dummy gate 130 and thesacrificial nanosheets 110, 114, according to an embodiment of thepresent disclosure.

The dummy gate 130 and the (SiGe) sacrificial nanosheets 110, 114 can beremoved by known etching processes including, for example, RIE orchemical oxide removal (COR). In a gate-last fabrication process, theremoved dummy gate 130 is thereafter replaced with a metal gate (notshown) as known in the art. It should be noted that the dummy gate 130and sacrificial nanosheets 110, 114 are removed selectively to the firstinner spacer 320 remaining on the second side of the semiconductorstructure 100.

Referring now to FIG. 9 , a cross-sectional view of the semiconductorstructure 100 after removing remaining portions of the first innerspacer 320 is shown, according to an embodiment of the presentdisclosure. In this embodiment, known etching processes such as, forexample, RIE or wet etching can be used to remove the remaining portionsof the first inner spacer 320 from the second or drain side of thesemiconductor structure 100. Second recesses 910 are formed in thesemiconductor structure 100 after removing the dummy gate 130 (FIG. 7 ),sacrificial nanosheets 110, 114 (FIG. 7 ), and first inner spacer 320(FIG. 8 ).

After removing the remaining portions of the first inner spacer 320(FIG. 8 ) from the drain side of the semiconductor structure 100, theasymmetric configuration of the second inner spacer 640 can be visiblyappreciated in the semiconductor structure 100. As shown in the figure,the second inner spacer 640 on the first (source) side of thesemiconductor structure 100 includes the protruding region 612 thatextends towards the second recesses 910, while the second inner spacer640 on the second (drain) side of the semiconductor structure 100 doesnot have the protruding region 612. As mentioned above, the protrudingregion 612 on the source side of the semiconductor structure 100provides a T-shaped inner spacer configuration capable of pinching-off asubsequently formed nitride layer, as will be described in detail below.

Referring now to FIGS. 10A-10B, a cross-sectional view of thesemiconductor structure 100 after deposition of a gate stack and metalfill is shown, according to an embodiment of the present disclosure. Asknown by those skilled in the art, in a replacement metal gate orgate-last fabrication process, the dummy gate 130 (FIG. 7 ) is replacedwith corresponding n-type or p-type metal gate stacks.

According to an embodiment, FIG. 10A depicts the semiconductor structure100 after deposition of gate dielectrics and work function metalssuitable for an n-type field effect transistor (NFET) device. For easeof illustration gate dielectrics are not depicted in the figure. In thisembodiment, a tri-layer gate metal stack formed by a doped transitionmetal layer 1020 located between an inner nitride layer 1010 and anouter nitride layer 1030 are conformally deposited in succession withinsecond recesses 910 (FIG. 9 ).

The inner nitride layer 1010 can be conformally formed within secondrecess 910 (FIG. 9 ) using any suitable deposition process. In someembodiments, the inner nitride layer 1010 is conformally deposited usingALD. In some embodiments, the inner nitride layer 1010 includes titaniumnitride (TiN). A thickness of the inner nitride layer 1010 can varybetween approximately 1 nm to approximately 2 nm.

The doped transition metal layer 1020 is formed on the inner nitridelayer 1010. In some embodiments, the doped transition metal layer 1020is deposited using ALD. In some embodiments, the doped transition metallayer 1020 includes an aluminum doped transition metal carbide. In someembodiments, the doped transition metal layer 1020 is formed using ahybrid ALD/CVD process having alternating pulses of a transition metalcontaining precursor and an aluminum carbide containing precursor. Inthis embodiment, the doped transition metal layer 1020 is made of, forexample, aluminum doped titanium carbide (TiAlC). A thickness of thedoped transition metal layer 1020 can vary between approximately 3 nm toapproximately 5 nm.

As known by those skilled in the art, the presence of aluminum (Al)containing metals can lower the device threshold voltage. By forming aT-shaped second inner spacer 640, the inner nitride layer 1010 ispinched-off on the source side of the semiconductor structure 100thereby preventing the deposition of Al-containing metals from the dopedtransition metal layer 1020. Accordingly, the inner spacer-gate metalstack configuration shown in FIG. 10A provides a lateral asymmetricchannel (LAC) structure with an asymmetric work function metaldistribution that causes threshold voltage to be higher on the first orsource side of the semiconductor structure 100. This may improve deviceshort channel performance without additional metal patterning.

The outer nitride layer 1030 can be conformally formed on the dopedtransition metal layer 1020 in a similar manner as the inner nitridelayer 1010. In some embodiments, the outer nitride layer 1030 isconformally deposited using ALD. In some embodiments, the outer nitridelayer 1030 includes titanium nitride (TiN). A thickness of the outernitride layer 1030 can vary between approximately 1 nm to approximately2 nm.

In some embodiments, a gate dielectric (not shown) is formed betweenchannel nanosheets 120 and the inner nitride layer 1010. The gatedielectric can be made of, for example, silicon oxide, silicon nitride,silicon oxynitride, boron nitride, high-k materials, or any combinationof these materials. Examples of high-k materials include but are notlimited to metal oxides such as hafnium oxide, hafnium silicon oxide,hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride,tantalum oxide, titanium oxide, barium strontium titanium oxide, bariumtitanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide,lead scandium tantalum oxide, and lead zinc niobate. The high-kmaterials can further include dopants such as lanthanum and aluminum. Insome embodiments, the gate dielectric can have a thickness varying fromapproximately 1 nm to approximately 3 nm.

According to another embodiment, FIG. 10B depicts the semiconductorstructure 100 after deposition of work function metals suitable for ap-type field effect transistor (PFET) device. In this embodiment, anitride layer 1012 is conformally deposited within second recesses 910(FIG. 9 ). The nitride layer 1012 can be conformally formed withinrecess 910 (FIG. 9 ) using any suitable deposition process. In someembodiments, the nitride layer 1012 is conformally deposited using ALD.In some embodiments, the nitride layer 1012 includes titanium nitride(TiN). A thickness of the nitride layer 1012 can vary betweenapproximately 3 nm to approximately 5 nm. As mentioned above withreference to FIG. 10A, a gate dielectric (not shown) can be formedbetween the channel nanosheets 120 and the nitride layer 1012.

In embodiments in which the semiconductor structure 100 is a PFETdevice, no aluminum (Al) containing metals are included in the gatemetal stack. Thus, in these embodiments, the asymmetric thresholdvoltage profile is caused by the difference in effective metal thicknessbetween the source side and the drain side of the semiconductorstructure 100. Stated differently, an effective thickness of the (metal)nitride layer 1012 on the source side of the semiconductor structure 100is less than an effective thickness of the nitride layer 1012 on thedrain side of the semiconductor structure 100. This reduction ineffective metal thickness on the source side of the semiconductorstructure 100 is caused by the protruding region 612 of the second innerspacer 640.

Accordingly, a lateral asymmetric channel (LAC) structure withasymmetric work function metal distribution and higher threshold voltageon the (first) source side can be achieved in embodiments in which thesemiconductor structure 100 is a PFET device. Similarly, to the NFETdevice described in FIG. 10A above, device short channel performance canbe improved without additional metal patterning.

With continued reference to FIGS. 10A-10B together, as known by thoseskilled in the art, after depositing the corresponding (p-type orn-type) work function metals within the second recesses 910 (FIG. 9 ) aconductive gate layer 1040 is deposited in the semiconductor structure100 above the uppermost nitride layer, as shown in the figure. Theconductive gate layer 1040 can be a metal (e.g., tungsten (W), titanium(Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr),cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin(Sn), silver (Ag), gold (Au), a conducting metallic compound material(e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide(TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC),tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO₂),cobalt silicide (CoSi), nickel silicide (NiSi)), transition metalaluminides (e.g. Ti₃Al, ZrAl), TaC, TaMgC, or any suitable combinationof these materials. In various embodiments, the conductive gate layer1040 may further include dopants that are incorporated during or afterdeposition. Any known deposition process can be used to form theconductive gate layer 1040. A planarization process, such as CMP, isgenerally conducted on the semiconductor structure 100 after depositionof the conductive gate layer 1040.

Finally, the proposed embodiments allow the formation of a semiconductorstructure with an asymmetric threshold voltage profile between sourceand drain regions that may improve device performance and enable furtherscaling of nanosheet technology.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method of forming a semiconductor structure,comprising: forming a nanosheet stack on a substrate, the nanosheetstack including an alternating sequence of sacrificial nanosheets andchannel nanosheets, the sacrificial nanosheets including secondnanosheets located between first nanosheets and third nanosheets, thefirst nanosheets and the third nanosheets having a first germaniumconcentration that is lower than a second germanium concentration of thesecond nanosheets; and selectively etching the sacrificial nanosheets,wherein the lower first germanium concentration causes the firstnanosheets and the third nanosheets to be etched slower than the secondnanosheets creating an indentation region on opposing sides of thenanosheet stack, the indentation region having a narrowing shape towardsremaining second nanosheets of the sacrificial nanosheets.
 2. The methodof claim 1, further comprising: forming a first inner spacer on opposingsides of the second nanosheets, the first inner spacer filling theindentation region; selectively removing first portions of the firstinner spacer located on a first side of the semiconductor structure toform first recesses, wherein second portions of the first inner spacerremain on a second side of the semiconductor structure opposing thesecond side; and forming a second inner spacer on the opposing sides ofthe sacrificial nanosheets and in direct contact with the channelnanosheets, a first portion of the second inner spacer substantiallyfilling the first recesses on the first side, the first portion of thesecond inner spacer on the first side having a protruding regionextending from a middle top surface of the first portion of the secondinner spacer towards remaining second layer of the sacrificialnanosheets.
 3. The method of claim 2, further comprising: forming asource region on the first side along sidewalls of the channelnanosheets and the second inner spacer and a drain region on the secondside along opposing sidewalls of the channel nanosheets and the secondinner spacer.
 4. The method of claim 3, further comprising: forming adummy gate above the nanosheet stack adjacent to an offset spacer;removing the dummy gate and the sacrificial nanosheets; removingremaining portions of the first inner spacer from the second side,wherein removing the dummy gate, the sacrificial nanosheets and theremaining portions of the first inner spacer creates second recess; andconformally depositing gate dielectrics and work function metals withinthe second recesses, the protruding region of the second inner spacerpinching off portions of the work function metals located on the firstside to create an asymmetric work function metal distribution thatincreases threshold voltage on the first side.
 5. The method of claim 4,further comprising: forming a protective organic planarizing layer onthe second side; removing the first inner spacer from the first side;and removing the protective organic planarizing layer from the secondside.
 6. The method of claim 1, wherein the channel nanosheets comprisesilicon and the first nanosheets, second nanosheets, and thirdnanosheets comprise silicon germanium, with the first germaniumconcentration of the first nanosheets and third nanosheets comprising25% germanium, and the second germanium concentration of the secondnanosheets comprising 35% germanium.
 7. The method of claim 2, whereinthe second inner spacer is selected from the group consisting of SiN,SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy.
 8. The method ofclaim 4, wherein the protruding region provides a T-shaped inner spacerwith a space between the protruding region and the channel nanosheetsthat is less than twice a thickness of a nitride layer of the workfunction metals.
 9. A method of forming a semiconductor structure,comprising: forming an inner spacer between channel nanosheets on asemiconductor substrate, a first portion of the inner spacer is locatedon a first side of the semiconductor structure and a second portion ofthe inner spacer is located on a second side of the semiconductorstructure opposing the first side, the first portion of the inner spaceron the first side including a protruding region extending outwards froma middle top surface of the first portion of the inner spacer; andforming a metal gate stack in direct contact with the inner spacer, thefirst portion of the inner spacer including the protruding regionpinching off the metal gate stack for increasing a threshold voltage onthe first side, the protruding region providing a T-shaped inner spacerwith a space between the protruding region and the channel nanosheetsbeing less than twice a thickness of an inner nitride layer in the metalgate stack.
 10. The method of claim 9, further comprising: forming asource region located on the first side and along sidewalls of thechannel nanosheets separated from the metal gate stack by the firstportion of the inner spacer; and forming a drain region located on thesecond side and along opposing sidewalls of the channel nanosheetsseparated from the metal gate stack by the second portion of the innerspacer on the second side.
 11. The method of claim 9, furthercomprising: forming a metal gate above the metal gate stack adjacent toan offset spacer.
 12. The method of claim 9, wherein the semiconductorstructure comprises an NFET device and the metal gate stack comprises atri-layer gate metal stack formed by a doped transition metal layerlocated between an inner nitride layer and an outer nitride layer, thedoped transition layer comprising an aluminum doped transition metalcarbide.
 13. The method of claim 12, wherein the protruding regionpinches off the inner nitride layer preventing deposition of the dopedtransition metal layer on the first side for increasing the thresholdvoltage.
 14. The method of claim 12, wherein the semiconductor structurecomprises a PFET device and the metal gate stack comprises the innernitride layer.
 15. The method of claim 12, wherein the protruding regionpinches off the inner nitride layer decreasing an effective metalthickness of the inner nitride layer on the first side for increasingthreshold voltage.
 16. The method of claim 9, wherein a material of thechannel nanosheets comprises silicon and a material of the inner spaceris selected from the group consisting of SiN, SiC, SiOC, SiCN, BN, SiBN,SiBCN, SiOCN, and SiOxNy.
 17. A method of forming a semiconductorstructure, comprising: forming a plurality of channel nanosheets abovean isolation region on a semiconductor substrate; forming an innerspacer between each of the plurality of channel nanosheets, a firstportion of the inner spacer is located on a first side of thesemiconductor structure, and a second portion of the inner spacer islocated on a second side of the semiconductor structure opposing thefirst side, the first portion of the inner spacer on the first sideincluding a protruding region extending outwards from a middle topsurface of the first portion of the inner spacer; and forming a metalgate stack separated from a source region located on the first side andalong sidewalls of the plurality of channel nanosheets by the firstportion of the inner spacer, the metal gate stack being separated from adrain region located on the second side and along opposing sidewalls ofthe plurality of channel nanosheets by the second portion of the innerspacer, the protruding region of the first portion of the inner spacerpinching off the metal gate stack for increasing a threshold voltage onthe first side, the protruding region providing a T-shaped inner spacerwith a space between the protruding region and the channel nanosheetsbeing less than twice a thickness of an inner nitride layer in the metalgate stack.
 18. The method of claim 17, further comprising: forming ametal gate above the metal gate stack adjacent to an offset spacer. 19.The method of claim 17, wherein the semiconductor structure comprises anNFET device and the metal gate stack comprises a tri-layer gate metalstack formed by a doped transition metal layer located between an innernitride layer and an outer nitride layer, the doped transition layercomprising an aluminum doped transition metal carbide.
 20. The method ofclaim 19, wherein the protruding region pinches off the inner nitridelayer preventing deposition of the doped transition metal layer on thefirst side for increasing the threshold voltage.
 21. The method of claim19, wherein the semiconductor structure comprises a PFET device and themetal gate stack comprises the inner nitride layer.
 22. The method ofclaim 19, wherein the protruding region pinches off the inner nitridelayer decreasing an effective metal thickness of the inner nitride layeron the first side for increasing the threshold voltage.
 23. The methodof claim 17, wherein a material of the plurality of channel nanosheetscomprises silicon and a material of the inner spacer is selected fromthe group consisting of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN,and SiOxNy.
 24. A method of forming a semiconductor structure,comprising: forming a nanosheet stack above a substrate, the nanosheetstack including a channel nanosheet disposed between a stack ofsacrificial nanosheets, the stack of sacrificial nanosheets includingfirst sacrificial nanosheets disposed on opposite sides and in directcontact with the channel nanosheet, second sacrificial nanosheets indirect contact with a side of the first sacrificial nanosheets opposinga side of the second sacrificial nanosheets in contact with the channelnanosheets and third sacrificial nanosheets above and in direct contactwith the second sacrificial nanosheets, wherein the first sacrificialnanosheets and the third sacrificial nanosheets have a first germaniumconcentration that is lower than a second germanium concentration of thesecond sacrificial nanosheets; selectively etching the stack ofsacrificial nanosheets to form an indentation region; forming a firstinner spacer partially filling the indentation region, the first innerspacer being located on opposite sides of the second sacrificialnanosheets and between the first and third sacrificial nanosheets;selectively removing portions of the first and third sacrificialnanosheets; selectively removing the first inner spacer from a firstside of the nanosheet stack, the first inner spacer remaining on asecond side of the nanosheet stack opposing the first side; anddepositing a second inner spacer on the first side of the nanosheetstack, wherein outer portions of the second inner spacer is aligned withthe channel nanosheet.
 25. The method of claim 24, further comprising:conducting a replacement metal gate process on the semiconductorstructure; and removing the first inner spacer from the second side ofthe nanosheet stack before completing the replacement metal gateprocess.